RDNA2 shaders to SPIR-V
PlayStation 5 shaders are RDNA2 machine code. PS5PCEM decodes the GFX10 families, builds a control-flow graph, and lowers the supported operations to SPIR-V 1.5 for Vulkan.
Repository notes through October 10, 2026
Decode
The frontend recognizes the scalar SOP1, SOP2, SOPK, SOPC, SOPP and SMEM encodings, the vector VOP1, VOP2, VOP3, VOP3P, VOPC and VINTRP encodings, MUBUF, MTBUF, FLAT, DS, MIMG and EXP. Architectural one-word and two-word bodies, optional literals and MIMG NSA address words are kept, so a later unsupported opcode does not desynchronize the stream.
An unrecognized opcode inside a known family becomes an unsupported instruction that still carries its family, its numeric opcode, the raw words and a reason. SDWA and DPP extension words keep their selectors, modifiers and lane masks. The decoder does not rename an opcode it does not know.
Control flow and the typed IR
Direct branch targets split the program into blocks. Forward merges, nested regions and backward edges are recorded separately. The live translator can emit from the decoded instructions. Setting PS5_GPU_SHADER_IR=1 selects the legalized typed IR. Setting PS5_GPU_SSA=1 adds phi and def-use state, constant folding and iterative dead-code elimination.
Acyclic selections become structured SPIR-V merges with phi values at the joins. Natural loops become loop merges. Irreducible control flow becomes a block-index dispatcher that keeps the VCC and EXEC predicates, so a lane that should have skipped a write still skips it. EXEC masks are reused inside a SPIR-V block and dropped at every label, because a value from one side of a branch does not dominate the other side.
What the October 9 suite measured
The scalar-call checkpoint of October 9 passed 259 of 259 GPU-analysis tests and 232 of 232 Vulkan tests. The RDNA2 suite passed 271 of 281, with the same ten existing failures and one reported leak. Those instruction probes do not establish a new frame rate for a game.
Multi-texel image loads, horizontal gathers, NGG fetch shaders and bounded scalar calls are implemented as their own paths and described on their own pages. Stores and descriptor combinations that were not in the measured set stay unsupported.
What is implemented
- Decode of the GFX10 scalar, vector, memory, image and export families, including literals and NSA words.
- Structured selections, natural loops, and a dispatcher for irreducible flow that preserves lane masks.
- Optional typed IR and SSA cleanup, selected with environment variables.
- SPIR-V 1.5 for the supported ALU, memory, image, interpolation and export operations.
What is still missing
- Ten existing RDNA2 suite failures remain, plus one reported leak.
- An unsupported opcode stops that lowering. It is not replaced with a guessed operation.
- The instruction tests are not a frame-rate result.
Related mechanisms
What these pages are