Texture detiling
PS5 textures are stored in GFX10 swizzle patterns, not in linear rows. PS5PCEM applies the address equations on the CPU, and on the GPU for the large 4, 8 and 16-byte surfaces that qualify.
Repository notes through October 10, 2026
The address equations
A tiled texture XORs the pixel coordinate with pipe, bank and sample bits so that neighbouring pixels land in different memory channels. PS5PCEM implements the GFX10 equations for linear layouts, Standard 256-byte, 4 KiB and 64 KiB tiles, partially resident 64 KiB tiles, depth Z_X and render-target R_X. The same contract covers mip tails and thick 3D blocks.
Up to sixteen mip levels are placed smallest first. Small levels share the exact 4 KiB and 64 KiB mip-tail positions. Three-dimensional resources use thick blocks and depth block-slices. Every subresource exposes one checked source-byte offset. Buffer, image, block-compressed, color-target and depth-target adapters allocate nothing and reject an overflow or a short range.
GPU detile and the CPU fallback
First-use uploads of large 4-byte standard 256-byte, 4 KiB and 64 KiB surfaces, and large linear surfaces, detile on the GPU. The compute kernel receives a pointer-free key and an 84-byte parameter block: block size, tail, pitch, slice, sample count and a 64-bit buffer offset, in a stable all-32-bit layout. Eight-byte and sixteen-byte 2D and 3D standard and PRT surfaces are in the same GPU family.
Other families stay on the CPU, including RB+ and MSAA. The Oberon equations for those include the sample bits, and the CPU path uses them. Falling back is a bandwidth cost. It is not a different pixel format. Diagnostics on a live draw report the family, the 3D block dimensions, the sample count, the mip-tail boundary and the guest allocation size.
Why detile shows up in frame time
A texture that is re-uploaded every frame pays the detile cost every frame. The page tracker, when it is enabled, lets an unchanged page stay resident so the detile is skipped. A texture the GPU itself rewrote still has to be invalidated. Detile does not replace that coherency rule.
Sampled views detile the mip range the descriptor names, including a non-zero base level. The Vulkan image's mip 0 is the view's base level in that case. Component swizzles that are still missing from the view path are a separate limitation from the address equation.
What is implemented
- GFX10 linear, Standard, PRT, depth and render-target address equations, including mip tails and 3D blocks.
- GPU compute detile for large 4, 8 and 16-byte 2D and 3D standard and PRT surfaces.
- CPU detile for the remaining families, including MSAA and RB+ sample bits.
- Checked subresource offsets that reject short ranges and overflows.
What is still missing
- MSAA and RB+ detile run on the CPU.
- Some component swizzles and layer views are still incomplete.
- A surface the CPU writes after upload has to be invalidated before it is sampled again.
Related mechanisms
What these pages are